The present invention relates to a semiconductor device. Particularly, the present invention is concerned with a technique that is applicable to a semiconductor device having external terminals formed by exposing leads partially from a back surface (a component side) of a resin sealing member.
As to semiconductor devices wherein a semiconductor chip with an integrated circuit formed thereon is sealed with resin, those of various package structures have been proposed and produced on a commercial basis. As one example, there is a semiconductor device called a QFN (Quad Flatpack Non-Leaded Package) type. This QFN type semiconductor device has a package structure wherein leads connected electrically to electrodes on a semiconductor chip are exposed as external terminals from a back surface of a resin sealing member. Therefore, the plane size of the semiconductor device can be reduced in comparison with, for example, a semiconductor device called a QFP (Quad Flatpack Package) type having a package structure wherein leads connected electrically to electrodes on a semiconductor chip are projected from side faces of a resin sealing member and are bent in a predetermined shape.
In the manufacture of a QFN type semiconductor device, a lead frame is used. The lead frame is fabricated by punching a metallic sheet with a precision press or by etching a metallic sheet to form predetermined patterns. The lead frame has plural product-forming areas partitioned by a frame body, which includes an outer frame and inner frames. In each product-forming area, there are a chip mounting portion (tab, die pad) for mounting a semiconductor chip thereon and plural leads having front end portions (end portions on one side) facing around the chip mounting portion. The chip mounting portion is supported by suspension leads extending from the frame body of the lead frame. End portions (front end portions) on one side and opposite end portions of the leads are supported by the frame body of the lead frame.
In the manufacture of a QFN type semiconductor device with use of such a lead frame, a semiconductor chip is fixed to the chip mounting portion of the lead frame, then electrodes on the semiconductor chip and the leads are electrically connected together through electrically conductive wires; and, thereafter, the semiconductor chip, wires, support member, and suspension leads are sealed with resin to form a resin sealing member, and, subsequently, unnecessary portions of the lead frame are cut off.
The resin sealing member in the QFN type semiconductor device is formed in the following manner by a transfer molding method which is suitable for mass production. The lead frame is positioned between an upper die half and a lower die half of a molding die so that a semiconductor chip, leads, a chip mounting portion, suspension leads, and bonding wires are arranged in the interior of each cavity in the molding die, followed by injection of a thermosetting resin into the cavity of the molding die.
An example of the QFN type semiconductor device is disclosed in Japanese Unexamined Patent Publication No. 2001-244399 (Patent Literature 1). In this publication, as methods for forming a resin sealing member, there are disclosed an individual type transfer molding method, wherein a lead frame having plural product-forming areas is used and semiconductor chips mounted in the product-forming areas are sealed with resin product-forming area by product-forming area, and a block molding type transfer molding method, wherein a lead frame having plural product-forming areas is used and semiconductor chips mounted in the product-forming areas are sealed with resin all together. Further, in the above-referenced publication, as a package structure, there is disclosed a so-called small tab structure wherein the plane size of the chip mounting area is set to be smaller than that of the semiconductor chip.
[Patent Literature 1]
Japanese Unexamined Patent Publication No. 2001-244399